Et r on Tech
EM636165
1M x 16 SDRAM
The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks
earlier (i.e. LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto
precharge function may be interrupted by a subsequent Read or Write command to the same bank
or the other active bank before the end of the burst length. It may be interrupted by a
BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read
command can occur on any clock cycle following a previous Read command (refer to the following
figure).
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ B
DOUTA
NOP
NOP
READ A
NOP
NOP
NOP
NOP
NOP
CAS# latency=1
DOUTB
DOUTB
DOUT B
DOUT B
2
0
1
3
0
t
, DQ's
CK1
CAS# latency=2
, DQ's
DOUTA
DOUTB
DOUTB
DOUT B
DOUT B
0
0
1
2
3
t
CK2
CAS# latency=3
, DQ's
DOUTA
0
DOUTB
DOUTB
1
DOUT B
DOUTB
0
3
t
2
CK3
Read Interrupted by a Read
(Burst Length = 4, CAS# Latency = 1, 2, 3)
The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt
comes from a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior
to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O
contention, a single cycle with high-impedance on the DQ pins must occur between the last read
data and the Write command (refer to the following three figures). If the data output of the burst read
occurs at the second clock of the burst write, the LDQM/UDQM must be asserted (HIGH) at least
one clock prior to the Write command to avoid internal bus contention.
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
DINB
NOP
COMMAND
DQ's
DINB
DINB
0
DOUT A
1
2
0
Must be Hi-Z before
the Write Command
: "H" or "L"
Read to Write Interval
≥
(Burst Length 4, CAS# Latency = 3)
Preliminary
7
Rev. 1.8
Nov 2001
ETRON [ ETRON TECHNOLOGY, INC. ]
