EtronTech
EM564081
Write Cycle 3
(CE2 Controlled)(See Note 4)
t
WC
Address
t
t
t
AS
WP
WR
WE#
CE1#
CE2
t
CW
t
CW
t
WHZ
D
OUT
t
LZ
t
t
DS
DH
D
(See Note 5)
VALID DATA IN
IN
Note:
1. WE# remains HIGH for the read cycle.
2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high
impedance.
3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain
at high impedance.
4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
Preliminary
January 2001
9
Rev 0.7
ETRON [ ETRON TECHNOLOGY, INC. ]
