ESMT
M24L48512SA
Thermal Resistance[7]
Parameter
θJA
Description
Thermal Resistance (Junction to Ambient)
Test Conditions
VFBGA
Unit
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
°C/W
55
θJC
°C/W
Thermal Resistance (Junction to Case)
17
AC Test Loads and Waveforms
Parameters
3.0V VCC
Unit
Ω
R1
R2
22000
22000
11000
1.50
Ω
RTH
VTH
Ω
V
Switching Characteristics (Over the Operating Range)[8]
–55
–60
–70
Parameter
Description
Unit
Min.
55[12]
5
Max.
Min.
60
Max.
Min.
Max.
Read Cycle
tRC
tAA
tOHA
tACE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
70
10
ns
ns
ns
ns
55
60
70
8
55
25
60
25
70
35
CE LOW
tDOE
ns
ns
ns
ns
ns
ns
OE LOW to Data Valid
OE LOW to Low Z[9, 10]
OE HIGH to High Z[9, 10]
CE LOW
tLZOE
tHZOE
tLZCE
tHZCE
5
2
5
2
5
5
25
25
25
25
0
25
0
25
10
CE HIGH
[12]
tSK
Address Skew
Write Cycle[11]
tWC
tSCE
Write Cycle Time
55
45
60
45
70
60
ns
ns
CE LOW
tAW
tHA
Address Set-up to Write End
Address Hold from Write End
45
0
45
0
55
0
ns
ns
Notes:
8. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of V CC(typ)/2, input pulse levels of 0V
to V CC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance.
9.
tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
10. High-Z and Low-Z parameters are characterized and are not 100% tested.
11. The internal write time of the memory is defined by the overlap of WE , CE = VIL. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be
referenced to the edge of the signal that terminates write.
12. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1 4/12
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
