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M13S64164A-5BG2Y 参数 Datasheet PDF下载

M13S64164A-5BG2Y图片预览
型号: M13S64164A-5BG2Y
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 4MX16, 0.7ns, CMOS, PBGA60, 8 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-60]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 49 页 / 1218 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M13S64164A (2Y)  
AC Operation Conditions & Timing Specifications  
AC Operation Conditions  
Parameter  
Symbol  
Min  
Max  
Unit  
V
Note  
Input High (Logic 1) Voltage, DQ, DQS and DM signals  
Input Low (Logic 0) Voltage, DQ, DQS and DM signals  
VIH(AC)  
VIL(AC)  
VID(AC)  
VREF + 0.31  
VREF - 0.31  
VDDQ+0.6  
V
0.7  
V
1
2
Input Differential Voltage, CLK and CLK inputs  
VIX(AC)  
0.5*VDDQ-0.2 0.5*VDDQ+0.2  
V
Input Crossing Point Voltage, CLK and CLK inputs  
Notes:  
1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .  
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of  
the same.  
AC Overshoot / Undershoot Specification  
Value  
Parameter  
Pin  
Unit  
-4 / -5 / -6  
1.5  
Address, Control  
Data, Strobe, Mask  
Address, Control  
Data, Strobe, Mask  
Address, Control  
Data, Strobe, Mask  
Address, Control  
Data, Strobe, Mask  
V
V
Maximum peak amplitude allowed for overshoot  
1.2  
1.5  
V
Maximum peak amplitude allowed for undershoot  
Maximum overshoot area above VDD  
1.2  
V
4.5  
V-ns  
V-ns  
V-ns  
V-ns  
2.4  
4.5  
Maximum undershoot area below VSS  
2.4  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Apr. 2012  
Revision : 1.0 8/49