ESMT
M13S5121632A
AC Timing Parameter & Specifications-continued
-5
Parameter
Symbol
Unit
Note
min
max
Half Clock Period
tHP
tQH
tCLmin or tCHmin
-
ns
ns
ns
ns
ns
ns
ns
ns
DQ-DQS output hold time
Data hold skew factor
t
HP-tQHS
-
-
tQHS
tRAS
tRC
0.5
ACTIVE to PRECHARGE command
Row Cycle Time
40
70K
55
-
-
-
-
AUTO REFRESH Row Cycle Time
ACTIVE to READ,WRITE delay
PRECHARGE command period
tRFC
tRCD
tRP
70
15
15
ACTIVE bank A to ACTIVE bank B
command
tRRD
10
-
ns
Write recovery time
tWR
tWTR
15
2
-
ns
tCK
us
Write data in to READ command delay
Average periodic refresh interval
Write preamble
-
tREFI
-
7.8
-
4
3
2
tWPRE
tWPST
tRPRE
tRPST
0.25
0.4
0.9
0.4
tCK
tCK
tCK
tCK
Write postamble
0.6
1.1
0.6
DQS read preamble
DQS read postamble
Clock to DQS write preamble setup
time
tWPRES
0
-
ns
Load Mode Register / Extended Mode
register cycle time
tMRD
tXSRD
tXSNR
10
200
75
-
-
-
ns
tCK
ns
Exit self refresh to READ command
Exit self refresh to non-READ
command
Autoprecharge write
recovery+Precharge time
tDAL
30
-
ns
Note :
1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ).
2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CLK edge.
A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS
.
4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
5. For command/address and CLK & CLK slew rate > 1.0V/ns.
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0 7/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
