ESMT
M13S5121632A
Pin Arrangement
x16
x16
VDD
1
66
65
64
63
62
61
60
VSS
DQ0
2
DQ15
VSS Q
DQ14
DQ13
VDD Q
VDD Q
DQ1
DQ2
VSS Q
DQ3
DQ4
VDD Q
DQ5
DQ6
VSS Q
DQ7
NC
3
4
5
6
7
DQ12
DQ11
VSS Q
DQ10
DQ9
VDD Q
DQ8
NC
8
59
58
57
56
55
54
53
52
51
50
49
48
9
10
11
12
13
66 PIN TSOP(II)
(400mil x 875mil)
14
15
16
17
18
19
20
21
22
23
24
25
(0.65 mm PIN PITCH)
VDD Q
LD QS
NC
VSS Q
UDQS
NC
VDD
NC
VRE F
VSS
UDM
CLK
CLK
CKE
NC
A12
A11
A9
LD M
WE
47
46
45
44
43
42
41
40
39
38
37
36
CAS
RAS
CS
NC
BA0
26
27
28
29
30
31
32
33
BA1
A10/AP
A0
A8
A7
A1
A6
A2
A5
A3
35
34
A4
VDD
VSS
Pin Description
Pin Name
Function
Pin Name
Function
Address inputs
- Row address A0~A12
DM is an input mask signal for write
data. LDM corresponds to the data
on DQ0~DQ7; UDM correspond to
the data on DQ8~DQ15.
A0~A12,
BA0,BA1
- Column address A0~ A9
A10/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
LDM, UDM
DQ0~DQ15
Data-in/Data-out
Clock input
CLK, CLK
CKE
Row address strobe
Column address strobe
Write enable
Clock enable
RAS
CAS
Chip select
CS
VDDQ
VSSQ
VREF
Supply Voltage for GDQ
Ground for DQ
WE
VSS
Ground
VDD
Power
Reference Voltage for SSTL-2
Bi-directional Data Strobe. LDQS
corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on
DQ8~DQ15.
LDQS, UDQS
NC
No connection
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0 3/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
