ESMT
M13S2561616A (2K)
AC Timing Parameter & Specifications (Note: 1~6, 9~10)
-4
-5
-6
Symbol
Unit
Note
Parameter
min
max
min
7.5
5
max
12
min
7.5
6
max
12
7.5
12
CL2
CL2.5
CL3
5
4
12
12
12
12
ns
ns
Clock period
tCK
5
12
6
12
CL4
4
12
5
12
6
12
tAC
-0.7
+0.7
-0.7
+0.7
-0.7
+0.7
DQ output access time from CLK/ CLK
CLK high-level width
tCH
tCL
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
CLK low-level width
DQS output access time from
CLK/ CLK
tDQSCK
-0.55
+0.55
1.25
-0.55
+0.55
1.25
-0.6
+0.6
1.25
ns
Clock to first rising edge of DQS delay
DQ and DM input setup time (to DQS)
DQ and DM input hold time (to DQS)
tDQSS
tDS
0.72
0.45
0.45
0.72
0.45
0.45
0.72
0.45
0.45
tCK
ns
ns
tDH
DQ and DM input pulse width (for each
input)
tDIPW
tIS
1.75
0.7
0.7
0.9
0.9
2.2
1.75
0.7
0.7
0.9
0.9
2.2
1.75
0.7
0.7
0.9
0.9
2.2
ns
ns
ns
ns
ns
ns
18
Address and Control input setup time
(fast)
15,
17~19
Address and Control input hold time
(fast)
15,
17~19
tIH
Address and Control input setup time
(slow)
tIS
16~19
16~19
18
Address and Control input hold time
(slow)
tIH
Control and Address input pulse width
(for each input)
tIPW
DQS input high pulse width
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.35
0.35
0.2
0.35
0.35
0.2
tCK
tCK
tCK
tCK
ns
DQS input low pulse width
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
Data strobe edge to output data edge
tDSH
0.2
0.2
0.2
tDQSQ
0.4
0.4
0.4
22
11
Data-out high-impedance time from
CLK/ CLK
tHZ
+0.7
+0.7
+0.7
ns
ns
Data-out low-impedance time from
CLK/ CLK
tLZ
-0.7
+0.7
-0.7
+0.7
-0.7
+0.7
11
tCLmin
or
tCLmin
or
tCLmin
or
Clock half period
tHP
ns
20,21
21
t
CHmin
t
CHmin
t
CHmin
DQ/DQS output hold time from DQS
Data hold skew factor
tQH
t
HP- tQHS
tHP- tQHS
t
HP- tQHS
ns
ns
tQHS
0.5
0.5
0.5
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2011
Revision : 1.6 9/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
