ESMT
M13S2561616A (2K)
IDD Specifications
Version
-5
Symbol
Unit
-4
90
-6
IDD0
80
70
100
10
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
120
10
110
10
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
40
30
30
30
30
30
30
25
20
80
70
60
180
180
150
5
160
160
140
5
140
140
130
5
IDD6
IDD7
230
220
210
Input / Output Capacitance
Delta Cap
(max)
Parameter
Package
Symbol
Min
Max
Unit
Note
Input capacitance (A0~A12, BA0~BA1,
CKE, CS , RAS , CAS , WE )
TSOP
BGA
2.5
2
4.5
4
pF
pF
pF
pF
pF
pF
pF
pF
CIN1
0.5
0.25
0.5
1,4
TSOP
BGA
2.5
2
4.5
4
CIN2
COUT
CIN3
1,4
Input capacitance (CLK, CLK )
TSOP
BGA
3.5
3
5.5
5
Data & DQS input/output capacitance
1,2,3,4
1,2,3,4
TSOP
BGA
3.5
3
5.5
5
Input capacitance (DM)
Notes:
0.5
1. These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and
DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameter is sampled. For speed grade -4 device, VDDQ = 2.6V ± 0.2V, VDD = 2.6V ± 0.2V; for other devices,
VDDQ = 2.5V ± 0.2V, VDD = 2.5V ± 0.2V. For all devices, f=100MHz, TA =25°C, VOUT(DC) = VDDQ/2, VOUT (peak to peak)
= 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace
matching at the board level).
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2011
Revision : 1.6 7/49