ESMT
M13S128324A
AC Operating Test Conditions
Parameter
Value
Unit
V
Input reference voltage for clock (VREF
Input signal maximum peak swing
Input signal minimum slew rate
Input levels (VIH/VIL)
)
0.5*VDDQ
1.5
V
1.0
V/ns
V
VREF+0.35/VREF-0.35
Input timing measurement reference level
Output timing reference level
VREF
VTT
V
V
AC Timing Parameter & Specifications
(VDD = 2.375V~2.75V, VDDQ=2.375V~2.75V, TA =0°C to 70°C )(Note)
(VDD = 2.5V~2.7V, VDDQ =2.5V~2.7V, TA = 0°C to 70°C (for speed -3.6))
-3.6
-4
-5
-6
Symbol
Parameter
Min Max Min Max Min Max Min Max
CL2
7.5
6.0
12
12
7.5
6.0
12
12
7.5
6.0
12
12
7.5
6.0
12
12
CL2.5
Clock Period
tCK
ns
ns
CL3
CL4
5.0
3.6
12
12
5.0
4.0
12
12
5.0
5.0
12
12
6.0
6.0
12
12
tAC
-0.6 +0.6 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7
Access time from CLK/ CLK
CLK high-level width
tCH
tCL
tDQSCK
tDQSS
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
-0.6 +0.6 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7
tCK
tCK
ns
CLK low-level width
Data strobe edge to clock edge
Clock to first rising edge of DQS delay
0.8
0.4
1.2
-
0.8
1.2
-
0.8
1.2
-
0.8
1.2
-
tCK
Data-in and DM setup time (to DQS)
tDS
0.45
0.45
0.45
ns
Data-in and DM hold time (to DQS)
tDH
tDIPW
tIS
0.4
1.75
0.9
0.9
2.2
0.4
0.4
0.2
0.2
-
0.45
1.75
0.9
0.9
2.2
0.4
0.4
0.2
0.2
-
0.45
1.75
1.0
1.0
2.2
0.4
0.4
0.2
0.2
-
0.45
1.75
1.0
1.0
2.2
0.4
0.4
0.2
0.2
-
ns
ns
ns
ns
ns
tCK
tCK
tCK
tCK
DQ and DM input pulse width (for each input)
-
-
-
-
Input setup time (fast slew rate)
Input hold time (fast slew rate)
Control and Address input pulse width
DQS input high pulse width
-
-
-
-
tIH
-
-
-
-
-
-
-
-
tIPW
tDQSH
tDQSL
tDSS
tDSH
0.6
0.6
-
0.6
0.6
-
0.6
0.6
-
0.6
0.6
-
DQS input low pulse width
DQS falling edge to CLK rising-setup time
DQS falling edge from CLK rising-hold time
-
-
-
-
Data strobe edge to output data edge
tDQSQ
tHZ
-
0.4
-
0.4
-
0.45
-
0.45
ns
ns
Data-out high-impedance window from
CLK/ CLK
-0.7 +0.7 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7
-0.7 +0.7 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7
Data-out low-impedance window from
CLK/ CLK
tLZ
ns
* speed -4 (CL3) must set VDD/VDDQ = 2.7V ± 0.1V
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8 7/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
