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M13S128324A-5LG 参数 Datasheet PDF下载

M13S128324A-5LG图片预览
型号: M13S128324A-5LG
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×32位×4银行双倍数据速率SDRAM [1M x 32 Bit x 4 Banks Double Data Rate SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 49 页 / 867 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M13S128324A  
DC Specifications  
Version  
Unit  
-
Note  
-
Parameter  
Symbol  
Test Condition  
-3.6  
-4  
-5  
-6  
Operation Current  
(One Bank Active)  
tRC = tRC (min) tCK = tCK (min)  
Active – Precharge  
IDD0  
235  
210  
175  
145  
mA  
-
Burst Length = 2 tRC = tRC (min),  
CL= 2.5 IOUT = 0mA,  
Active-Read- Precharge  
Operation Current  
(One Bank Active)  
IDD1  
IDD2P  
IDD2N  
IDD3P  
245  
40  
220  
40  
190  
40  
180  
40  
mA  
mA  
mA  
mA  
-
-
-
-
Precharge Power-down  
Standby Current  
CKE VIL(max), tCK = tCK (min),  
All banks idle  
CKE VIH(min), CS ≥  
VIH(min), tCK = tCK (min)  
Idle Standby Current  
135  
60  
120  
55  
115  
50  
95  
Active Power-down Standby  
Current  
All banks ACT, CKE VIL(max),  
tCK = tCK (min)  
45  
One bank; Active-Precharge, tRC  
Active Standby Current  
IDD3N = tRAS(max),  
tCK = tCK (min)  
150  
130  
120  
110  
mA  
-
Burst Length = 2, CL= 2.5 , tCK  
CK (min), IOUT = 0Ma  
=
=
Operation Current (Read)  
Operation Current (Write)  
IDD4R  
IDD4W  
440  
470  
400  
430  
350  
380  
300  
330  
mA  
mA  
-
-
t
Burst Length = 2, CL= 2.5 , tCK  
CK (min)  
t
Auto Refresh Current  
Self Refresh Current  
IDD5  
IDD6  
320  
3
290  
3
270  
3
250  
3
mA  
mA  
-
tRC tRFC(min)  
CKE 0.2V  
1
Note 1. Enable on-chip refresh and address counters.  
AC Operation Conditions & Timing Specification  
AC Operation Conditions  
Parameter  
Symbol  
Min  
Max  
-
Unit  
Note  
Input High (Logic 1) Voltage, DQ, DQS and DM signals  
Input Low (Logic 0) Voltage, DQ, DQS and DM signals  
VIH(AC)  
VIL(AC)  
VID(AC)  
VREF + 0.35  
V
V
V
-
-
-
VREF - 0.35  
VDDQ+0.6  
0.7  
1
Input Different Voltage, CLK and CLK inputs  
VIX(AC)  
0.5*VDDQ-0.2 0.5*VDDQ+0.2  
V
2
Input Crossing Point Voltage, CLK and CLK inputs  
Note1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .  
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of  
the same.  
Input / Output Capacitance  
(VDD = 2.375V~2.75V, VDDQ =2.375V~2.75V, TA = 25°C , f = 1MHz)  
(VDD = 2.5V~2.7V, VDDQ =2.5V~2.7V, TA = 25°C , f = 1MHz (for speed -3.6))  
(VDD = 2.6V~2.8V, VDDQ =2.6V~2.8V, TA = 25°C , f = 1MHz [only for speed -4(CL3)])  
Parameter  
Symbol  
CIN1  
Min  
1
Max  
4
Unit  
pF  
Input capacitance(A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE )  
CIN2  
1
5
pF  
Input capacitance (CLK, CLK )  
Data & DQS input/output capacitance  
Input capacitance (DM)  
COUT  
CIN3  
1
1
6.5  
6.5  
pF  
pF  
Elite Semiconductor Memory Technology Inc.  
Publication Date : May. 2007  
Revision : 1.8 6/49