ESMT
M13S128168A (2N)
Automotive Grade
IDD Specifications
Version
-5
Symbol
Unit
-4
90
-6
IDD0
80
70
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
110
8
100
8
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
8
40
35
30
40
35
30
20
15
15
70
65
60
190
160
180
3
170
150
160
3
150
140
140
3
IDD6
IDD7
250
230
210
Input / Output Capacitance
Delta Cap
(max)
Parameter
Package
Symbol
Min
Max
Unit
Note
Input capacitance (A0~A11, BA0~BA1,
CKE, CS , RAS , CAS , WE )
TSOP
BGA
1.5
TBD
1.5
5
TBD
5
pF
pF
pF
pF
pF
pF
pF
pF
CIN1
0.5
0.25
0.5
1,4
TSOP
BGA
CIN2
COUT
CIN3
1,4
Input capacitance (CLK, CLK )
TBD
1.5
TBD
5
TSOP
BGA
Data & DQS input/output capacitance
1,2,3,4
1,2,3,4
TBD
1.5
TBD
5
TSOP
BGA
Input capacitance (DM)
Notes:
0.5
TBD
TBD
1. These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and
DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameter is sampled. VDDQ = 2.5V ± 0.2V, VDD = 2.5V ± 0.2V. For all devices, f=100MHz, TA =25°C, VOUT(DC) =
VDDQ/2, VOUT (peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in
loading (to facilitate trace matching at the board level).
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.1 7/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
