ESMT
SDRAM
M12S64322A
512K x 32 Bit x 4 Banks
Synchronous DRAM
FEATURES
y
y
y
y
JEDEC standard 2.5V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
ORDERING INFORMATION
Product No.
MAX FREQ. PACKAGE COMMENTS
M12S64322A-6TG
M12S64322A-7TG
M12S64322A-6BG
M12S64322A-7BG
166MHz
143MHz
166MHz
143MHz
TSOPII
TSOPII
90BGA
90BGA
Pb-free
Pb-free
Pb-free
Pb-free
y
y
y
y
DQM for masking
Auto & self refresh
15.6μs refresh interval
GENERAL DESCRIPTION
The M12S64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
PIN ARRANGEMENT
Top View
VDD
DQ0
VDDQ
DQ1
DQ2
VSS Q
DQ3
DQ4
VDDQ
DQ5
DQ6
VSS
1
2
3
4
5
6
7
8
9
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
DQ15
VSS Q
DQ14
DQ13
VDDQ
DQ12
DQ11
VSS Q
DQ10
DQ9
VDDQ
DQ8
N C
10
11
VSS Q 12
DQ7
13
14
NC
VDD 15
DQM0 16
WE 17
CAS
RAS
CS
VSS
DQM1
N C
18
19
20
N C
CLK
CKE
A9
NC
BA0
21
22
23
24
25
26
27
28
29
30
31
32
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
A8
A7
BA1
A6
A10/AP
A0
A5
A4
A1
A3
A2
DQM3
VSS
DQM2
VDD
N C
NC
DQ31
VDDQ
DQ30
DQ29
VSS Q
DQ28
DQ27
VDDQ
DQ26
DQ25
VSS Q
DQ24
VSS
DQ16
VSS Q
DQ17 33
DQ18 34
VDDQ 35
DQ19 36
DQ20
VSS Q
DQ21
DQ22
VDDQ
37
38
39
40
41
DQ23 42
VDD
43
86Pin TSOP(II)
(400mil x 875mil)
(0.5mm Pin pitch)
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0 2/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
