ESMT
M12S64322A
AC OPERATING TEST CONDITIONS (VDD = 2.5V± 0.2V ，TA = 0 to 70°C)
Parameter
Input levels (Vih/Vil)
Value
0.9 * VDDQ / 0.2
0.5 * VDDQ
tr/tf = 1/1
Unit
V
Input timing measurement reference level
Input rise and fall-time
V
ns
V
Output timing measurement reference level
Output load condition
0.5 * VDDQ
See Fig. 2
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-6
-7
Row active to row active delay
tRRD(min)
12
14
20
ns
ns
1
1
tRCD(min)
18
RAS to CAS delay
Row precharge time
tRP(min)
18
42
20
42
ns
ns
1
1
tRAS(min)
tRAS(max)
tRC(min)
Row active time
100
us
Row cycle time
@ Operating
60
63
ns
1
2
2
2
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
tCDL(min)
tRDL(min)
tBDL(min)
1
2
1
CLK
CLK
CLK
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0 7/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
