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M12S16161A-6BG 参数 Datasheet PDF下载

M12S16161A-6BG图片预览
型号: M12S16161A-6BG
PDF下载: 下载PDF文件 查看货源
内容描述: 512K X 16位X 2Banks同步DRAM [512K x 16Bit x 2Banks Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 28 页 / 619 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M12S16161A  
AC OPERATING TEST CONDITIONS (VDD=2.375~2.625V,TA= 0 to 70°C )  
Parameter  
Value  
0.9 x VDDQ / 0.2  
0.5 x VDDQ  
tr / tf = 1 / 1  
0.5 x VDDQ  
See Fig.2  
Unit  
V
V
ns  
V
Input levels (Vih/Vil)  
Input timing measurement reference level  
Input rise and fall time  
Output timing measurement reference level  
Output load condition  
OPERATING AC PARAMETER  
(AC operating conditions unless otherwise noted)  
Version  
Parameter  
Symbol  
Unit  
Note  
-6  
-7  
Row active to row active delay  
tRRD(min)  
tRCD(min)  
12  
14  
ns  
ns  
1
1
18  
20  
RAS to CAS delay  
Row precharge time  
tRP(min)  
tRAS(min)  
18  
36  
100  
54  
1
20  
42  
ns  
ns  
1
1
Row active time  
tRAS(max)  
tRC(min)  
us  
Row cycle time  
63  
ns  
1
2
2
2
3
Last data in to new col. Address delay  
Last data in to row precharge  
Last data in to burst stop  
tCDL(min)  
CLK  
CLK  
CLK  
CLK  
tRDL(min)  
2
tBDL(min)  
1
Col. Address to col. Address delay  
tCCD(min)  
1
CAS latency=3  
CAS latency=2  
2
Number of valid output data  
ea  
4
1
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and  
then rounding off to the next higher integer.  
2.  
Minimum delay is required to complete write.  
3. All parts allow every cycle column address change.  
4. In case of row precharge interrupt, auto precharge and read burst stop.  
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jul. 2007  
Revision : 1.2 5/28