ESMT
M12S128324A
Version
Parameter
Symbol
Unit
Note
-6
-7
Col. address to col. address delay
tCCD(min)
1
2
CLK
ea
3
4
CAS latency = 3
Number of valid
Output data
CAS latency = 2
CAS latency = 1
1
0
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
-6
-7
Parameter
Symbol
Unit
Note
Min
6
Max
Min
7
Max
CAS latency = 3
CLK cycle time
tCC
1000
1000
ns
1
CAS latency = 2
CAS latency = 1
CAS latency = 3
CAS latency = 2
CAS latency = 1
CAS latency = 3
CAS latency = 2
CAS latency = 1
8
8.6
20
20
5.8
7
6
7
CLK to valid
output delay
tSAC
ns
ns
1,2
2
17
18
2
2
2
2
2
2
1
1
2
2
Output data
hold time
tOH
2
CLK high pulsh width
CLK low pulsh width
Input setup time
tCH
tCL
2.5
2.5
2
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
tSH
tSLZ
Input hold time
1
CLK to output in Low-Z
1
CAS latency = 3
CAS latency = 2
CAS latency = 1
5.8
7
6
7
CLK to output
in Hi-Z
tSHZ
ns
-
17
18
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 7/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
