ESMT
M12S128324A
AC OPERATING TEST CONDITIONS [VDD = 2.5V± 0.2V, VDD = 2.375V~2.625V (for -6), TA = 0 to 70°C]
Parameter
Input levels (Vih/Vil)
Value
0.9XVDDQ / 0.2
0.5xVDDQ
Unit
V
Input timing measurement reference level
Input rise and fall-time
V
tr/tf = 1/1
ns
V
Output timing measurement reference level
Output load condition
0.5xVDDQ
See Fig. 2
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-6
-7
Row active to row active delay
RAS to CAS delay
tRRD(min)
12
14
ns
ns
1
1
tRCD(min)
18
18
42
18
20
42
Row precharge time
tRP(min)
ns
ns
us
ns
1
1
tRAS(min)
Row active time
tRAS
100
(max)
Row cycle time
@ Operating
tRC(min)
60
75
70
84
1
@ Auto Refresh
tRFC(min)
tCDL(min)
tRDL(min)
tBDL(min)
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
1
2
1
CLK
CLK
CLK
2
2
2
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 6/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
