ESMT
M12L64164A (2M)
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = 0 to 70°C
VERSION
PARAMETER
SYMBOL
TEST CONDITION
UNIT NOTE
-5
-6
-7
Burst Length = 1, tRC ≥ tRC(min), IOL = 0 mA,
tCC = tCC (min)
Operating Current
(One Bank Active)
ICC1
100
85
85
mA
mA
1,2
ICC2P
2
1
CKE ≤ VIL(max), tCC = tCC (min)
CKE & CLK ≤ VIL(max), tCC = ∞
Precharge Standby Current
in power-down mode
ICC2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = tCC (min)
Input signals are changed one time during 2CLK
ICC2N
20
10
Precharge Standby Current
in non power-down mode
mA
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
input signals are stable
ICC2NS
ICC3P
10
10
CKE ≤ VIL(max), tCC = tCC (min)
CKE & CLK ≤ VIL(max), tCC = ∞
Active Standby Current
in power-down mode
ICC3PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns
Input signals are changed one time during 2clks
All other pins ≥ VDD-0.2V or ≤ 0.2V
ICC3N
ICC3NS
ICC4
Active Standby Current
in non power-down mode
(One Bank Active)
30
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
input signals are stable
25
mA
mA
Operating Current
(Burst Mode)
IOL = 0 mA, Page Burst, All Bank active
Burst Length = 4, CAS Latency = 3
tRFC ≥ tRFC(min), tCC = tCC(min)
1,2
180
180
150
140
140
Refresh Current
ICC5
ICC6
150
1
mA
mA
Self Refresh Current
CKE ≤ 0.2V
Note:
1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2012
Revision: 1.6 4/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
