欢迎访问ic37.com |
会员登录 免费注册
发布采购

M12L2561616A-7BIG 参数 Datasheet PDF下载

M12L2561616A-7BIG图片预览
型号: M12L2561616A-7BIG
PDF下载: 下载PDF文件 查看货源
内容描述: 4M ×16位×4银行同步DRAM [4M x 16 Bit x 4 Banks Synchronous DRAM]
分类和应用: 存储内存集成电路动态存储器
文件页数/大小: 45 页 / 921 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
 浏览型号M12L2561616A-7BIG的Datasheet PDF文件第1页浏览型号M12L2561616A-7BIG的Datasheet PDF文件第2页浏览型号M12L2561616A-7BIG的Datasheet PDF文件第3页浏览型号M12L2561616A-7BIG的Datasheet PDF文件第4页浏览型号M12L2561616A-7BIG的Datasheet PDF文件第6页浏览型号M12L2561616A-7BIG的Datasheet PDF文件第7页浏览型号M12L2561616A-7BIG的Datasheet PDF文件第8页浏览型号M12L2561616A-7BIG的Datasheet PDF文件第9页  
ESMT  
M12L2561616A  
Operation Temperature Condition -40~85°C  
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V TA = -40 to 85°C )  
Parameter  
Input levels (Vih/Vil)  
Value  
2.4/0.4  
1.4  
Unit  
V
Input timing measurement reference level  
Input rise and fall-time  
V
tr/tf = 1/1  
1.4  
ns  
V
Output timing measurement reference level  
Output load condition  
See Fig. 2  
(Fig. 1) DC Output Load Circuit  
(Fig. 2) AC Output Load Circuit  
OPERATING AC PARAMETER  
(AC operating conditions unless otherwise noted)  
Version  
Parameter  
Symbol  
Unit  
Note  
-6  
12  
18  
18  
-7  
14  
20  
20  
Row active to row active delay  
tRRD(min)  
tRCD(min)  
ns  
ns  
1
1
RAS to CAS delay  
Row precharge time  
tRP(min)  
ns  
ns  
1
1
tRAS(min)  
42  
45  
Row active time  
tRAS(max)  
tRC(min)  
100  
us  
ns  
@ Operating  
1
60  
60  
63  
70  
Row cycle time  
@ Auto refresh tRFC(min)  
ns  
tCK  
tCK  
tCK  
ms  
1,5  
2
Last data in to col. address delay  
Last data in to row precharge  
Last data in to burst stop  
tCDL(min)  
tRDL(min)  
tBDL(min)  
tREF(max)  
1
2
2
1
2
Refresh period (8,192 rows)  
64  
6
Elite Semiconductor Memory Technology Inc.  
Publication Date: May 2008  
Revision: 1.2 5/45