M12L16161A
Mode Register
11 10
9
0
9
1
8
7
1
7
0
6
6
5
5
4
4
3
2
2
1
0
0
0
0
0
JEDEC Standard Test Set (refresh counter test)
11 10
8
3
WT
1
BL
x
x
0
LTMODE
Burst Read and Single Write (for Write
Through Cache)
11 10
9
8
7
6
5
4
3
2
1
0
1
0
Use in future
11 10
9
x
9
0
8
1
8
0
7
1
7
0
6
v
6
5
v
5
4
v
4
3
v
3
2
v
2
1
v
1
BL
0
v
0
x
x
Vender Specific
v =Valid
11 10
0
0
LTMODE
WT
Mode Register Set
x =Don’t care
Bit2-0
000
001
010
011
100
101
110
111
WT=0
WT=1
1
2
4
8
R
R
R
1
2
4
Burst length
8
R
R
R
R
Full page
0
1
Sequential
Interleave
Wrap type
Bits6-4
CAS Latency
000
001
010
011
100
101
110
111
R
R
2
Latency mode
3
R
R
R
R
Mode Register Write Timing
Remark R : Reserved
CLOCK
CKE
CS
RAS
CAS
WE
A0-A11
Mod e Regis ter Write
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.8
:
Revis ion 1.3u