ESMT
M12L128324A
Operation temperature condition -40°C~85°C
SDRAM
1M x 32 Bit x 4 Banks
Synchronous DRAM
FEATURES
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JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (1, 2 & 3 )
ORDERING INFORMATION
Product No.
MAX FREQ. PACKAGE COMMENTS
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
M12L128324A-6TIG
M12L128324A-7TIG
M12L128324A-6BIG
M12L128324A-7BIG
166MHz
143MHz
166MHz
143MHz
86L TSOPII
86L TSOPII
90 FBGA
Pb-free
Pb-free
Pb-free
Pb-free
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90 FBGA
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2006
Revision: 1.1 2/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
