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M12L128168A_1 参数 Datasheet PDF下载

M12L128168A_1图片预览
型号: M12L128168A_1
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×16位×4银行同步DRAM [2M x 16 Bit x 4 Banks Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 22 页 / 361 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M12L128168A  
Operation temperature condition -40°C ~85°C  
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3VTA = -40 to 85°C )  
Parameter  
Input levels (Vih/Vil)  
Value  
2.4/0.4  
1.4  
Unit  
V
Input timing measurement reference level  
Input rise and fall-time  
V
tr/tf = 1/1  
1.4  
ns  
V
Output timing measurement reference level  
Output load condition  
See Fig. 2  
Vtt = 1.4V  
3.3V  
50 Ω  
1200  
VOH (DC) =2.4V , IOH = -2 mA  
VOL (DC) =0.4V , IOL = 2 mA  
Output  
Output  
Z0 =50 Ω  
50pF  
50pF  
870 Ω  
(Fig. 1) DC Output Load Circuit  
(Fig. 2) AC Output Load Circuit  
OPERATING AC PARAMETER  
(AC operating conditions unless otherwise noted)  
Version  
Parameter  
Symbol  
Unit  
Note  
-5  
10  
15  
15  
-6  
12  
18  
18  
-7  
14  
20  
20  
Row active to row active delay  
tRRD(min)  
tRCD(min)  
ns  
ns  
1
1
RAS to CAS delay  
Row precharge time  
tRP(min)  
ns  
ns  
1
1
tRAS(min)  
38  
40  
42  
Row active time  
tRAS(max)  
tRC(min)  
100  
58  
us  
ns  
1
53  
55  
63  
70  
@ Operating  
Row cycle time  
@ Auto refresh tRFC(min)  
60  
1
ns  
tCK  
tCK  
tCK  
ms  
1,5  
2
Last data in to col. address delay  
Last data in to row precharge  
Last data in to burst stop  
tCDL(min)  
tRDL(min)  
tBDL(min)  
tREF(max)  
2
2
1
2
Refresh period (4,096 rows)  
64  
6
Elite Semiconductor Memory Technology Inc.  
Publication Date: Oct. 2007  
Revision: 1.2 5/43