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M12L128168A-6TVAG2N 参数 Datasheet PDF下载

M12L128168A-6TVAG2N图片预览
型号: M12L128168A-6TVAG2N
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-54]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 46 页 / 687 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M12L128168A (2N)  
Automotive Grade  
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V)  
Parameter  
Input levels (Vih/Vil)  
Value  
Unit  
V
2.4/0.4  
1.4  
Input timing measurement reference level  
Input rise and fall-time  
V
tr/tf = 1/1  
1.4  
ns  
V
Output timing measurement reference level  
Output load condition  
See Fig. 2  
Vtt = 1.4V  
3.3V  
50 Ω  
1200  
VOH (DC) =2.4V , IOH = -2 mA  
VOL (DC) =0.4V , IOL = 2 mA  
Output  
Output  
Z0 =50 Ω  
50pF  
50pF  
870 Ω  
(Fig. 1) DC Output Load Circuit  
(Fig. 2) AC Output Load Circuit  
OPERATING AC PARAMETER  
(AC operating conditions unless otherwise noted)  
Version  
Parameter  
Symbol  
Unit  
Note  
-5  
10  
15  
-6  
12  
18  
-7  
14  
21  
Row active to row active delay  
tRRD(min)  
ns  
ns  
1
1
t
RCD(min)  
RAS to CAS delay  
Row precharge time  
tRP(min)  
15  
40  
18  
42  
21  
42  
ns  
ns  
1
1
tRAS(min)  
Row active time  
t
RAS(max)  
tRC(min)  
RFC(min)  
100  
60  
us  
ns  
@ Operating  
Row cycle time  
55  
55  
63  
63  
1
@ Auto refresh  
t
60  
ns  
1,5  
Last data in to col. address delay  
tCDL(min)  
tRDL(min)  
tBDL(min)  
1
2
CLK  
CLK  
CLK  
ms  
2
2
2
6
6
3
Last data in to row precharge  
Last data in to burst stop  
1
t
REF(max)  
Refresh period (4,096 rows) for TA 85℃  
Refresh period (4,096 rows) for TA85(VA grade only)  
Col. address to col. address delay  
64  
16  
1
tREF(max)  
tCCD(min)  
ms  
CLK  
CAS latency = 3  
CAS latency = 2  
2
1
Number of valid Output data  
ea  
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then  
rounding off to the next higher integer.  
2. Minimum delay is required to complete write.  
3. All parts allow every cycle column address change.  
4. In case of row precharge interrupt, auto precharge and read burst stop.  
5. A new command may be given tRFC after self refresh exit.  
6. A maximum of eight consecutive AUTO REFRESH commands (with tRFC(min)) can be posted to any given SDRAM, and  
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is  
8x15.6μ s (8 x 3.9μs for VA grade with TA85).  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jun. 2012  
Revision: 1.1 6/46