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M12L128168A-5TIG2L 参数 Datasheet PDF下载

M12L128168A-5TIG2L图片预览
型号: M12L128168A-5TIG2L
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 8MX16, 4.5ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-54]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 45 页 / 689 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M12L128168A (2L)  
Operation Temperature Condition -40°C~85°C  
AC CHARACTERISTICS (AC operating condition unless otherwise noted)  
-5  
-6  
-7  
Parameter  
Symbol  
Unit  
Note  
MIN  
MAX MIN  
MAX MIN  
MAX  
CAS latency = 3  
5
10  
-
6
7
CLK cycle time  
tCC  
ns  
1
1000  
1000  
1000  
CAS latency = 2  
CAS latency = 3  
CAS latency = 2  
CAS latency = 3  
CAS latency = 2  
10  
10  
4.5  
-
-
5.4  
-
-
5.4  
CLK to valid  
output delay  
tSAC  
ns  
ns  
1,2  
2
-
6
6
6
2
-
2
-
2
-
Output data  
hold time  
tOH  
2
-
2
-
2
-
CLK high pulse width  
CLK low pulse width  
Input setup time  
tCH  
tCL  
2
-
2.5  
2.5  
1.5  
1
-
2.5  
2.5  
1.5  
1
-
ns  
ns  
ns  
ns  
ns  
3
3
3
3
2
2
-
-
-
-
-
-
tSS  
tSH  
tSLZ  
1.5  
1
Input hold time  
-
-
-
CLK to output in Low-Z  
1
-
1
-
1
-
CAS latency = 3  
CAS latency = 2  
-
4.5  
-
5.4  
-
5.4  
CLK to output  
in Hi-Z  
tSHZ  
ns  
-
-
6
-
6
-
6
Note:  
1. Parameters depend on programmed CAS latency.  
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.  
3. Assumed input rise and fall time (tr & tf) =1ns.  
If tr & tf is longer than 1ns. transient time compensation should be considered.  
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: May 2012  
Revision: 1.1 6/45