M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
FUNCTIONAL BLOCK DIAGRAM
WE
DATA-IN BUFFER
RAS
CONTROL
LOGIC
IO0
:
IO15
16
CASL
CASH
CLOCK
GENERATOR
DATA-OUT
BUFFER
OE
COLUMN
DECODER
COLUMN
ADDRESS
BUFFER
10
10
16
A0
A1
1024
16
A2
A3
SENSE AMPLIFIERS
I/O GATING 8
REFRESH
CONTROLER
A4
A5
A6
A7
A8
A9
1024 x16
REFRESH
COUNTER
10
1024 x 1024 x 16
MEMORY
1024
ROW.
ADDRESS
ARRAY
10
10
BUFFERS(10)
VCC
VSS
VBB GENERATOR
PIN DESCRIPTIONS
PIN NO.
PIN NAME
TYPE
DESCRIPTION
(SOJ Package)
Address Input
17~20, 23~28
A0~A9
Input
Row Address : A0~A9
Column Address : A0~A9
14
30
31
13
29
Input
Input
Input
Input
Input
Row Address Strobe
RAS
CASH
CASL
WE
Column Address Strobe / Upper Byte Control
Column Address Strobe / Lower Byte Control
Write Enable
Output Enable
OE
2~5,7~10,33~36,38~41 I/O0 ~ I/O15
Input / Output Data Input / Output
CC
1,6,21
22,37,42
V
Supply
Ground
-
Power, (5V or 3.3V)
Ground
SS
V
11,12,15,16,32
NC
No Connect
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.3
2/16
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
