EFST
F49L400UA/F49L400BA
7. FUNCTIONAL DESCRIPTION
7.1 Device operation
This section describes the requirements and use
of the device bus operations, which are initiated
through the internal command register. The
register is composed of latches that store the
command, address and data information needed
to execute the command. The contents of the
register serve as inputs to the internal state
machine. The state machine outputs dictate the
function
of
the
device.
The
F49L400UA/F49L400BA features various bus
operations as Table 3.
Table 3. F49L400UA/F49L400BA Operation Modes Selection
ADDRESS
A8
A17 A11
A5
|
DESCRIPTION
DQ0~DQ7
OE
RESET
CE
WE
|
|
|
A9
A6
A1 A0
A12 A10
A7
A2
L, Vss±
0.3V(3)
Reset(3)
X
X
X
X
High Z
Read
L
L
L
L
H
H
H
L
H
H
H
AIN
AIN
X
Dout
DIN
Write
Output Disable
H
High Z
V
0.3V
CC±±
VCC±±
0.3V
Standby
X
X
X
High Z
Sector Protect(2)
L
L
H
H
X
L
L
X
VID
SA
SA
X
X
X
X
X
L
X
X
H
H
L
L
DIN
DIN
DIN
Sector Unprotect(2)
Temporary sector unprotect
Auto-select
VID
X
H
X
VID
AIN
See Table 4
Notes:
1. L= Logic Low = VIL, H= Logic High = VIH, X= Don't Care, SA= Sector Address, VID=11.5V to 12.5V.
AIN= Address In, DIN = Data In, Dout = Data Out.
2. The sector protect and unprotect functions may also be implemented via programming equipment.
3. See “Reset Mode” section.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.1 5/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
