EFST
F49L400UA/F49L400BA
4. PIN CONFIGURATIONS
4.1 48-pin TSOP
A16
48
1
A15
A14
A13
A12
A11
A10
A9
BYTE
47
2
GND
46
3
DQ15/A-1
45
4
DQ7
44
5
DQ14
43
6
DQ6
42
7
DQ13
41
8
A8
DQ5
40
9
N C
N C
WE
RESET
N C
N C
RY/BY
N C
A17
A7
DQ12
39
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ4
38
F49L400U/BA
VCC
37
DQ11
36
DQ3
35
DQ10
34
DQ2
33
DQ9
32
DQ1
31
DQ8
30
A6
DQ0
29
A5
OE
28
A4
GND
27
A3
CE
26
A2
A0
25
A1
4.2 Pin Description
Symbol
A0~A17
Pin Name
Address Input
Functions
To provide memory addresses.
To output data when Read and receive data when Write.
DQ0~DQ14 Data Input/Output
The outputs are in tri-state when OE or CE is high.
Q15 (Word mode) /
DQ15/A-1
To bi-direction date I/O when BYTE is High
To input address when BYTE is Low
LSB addr (Byte Mode)
Chip Enable
Output Enable
Write Enable
Reset
CE
To activate the device when CE is low.
To gate the data output buffers.
OE
To control the Write operations.
WE
Hardware Reset Pin/Sector Protect Unprotect
RESET
BYTE
Word/Byte selection input To select word mode or byte mode
Ready/Busy
To check device operation status
To provide power
RY/ BY
VCC
Power Supply
Ground
GND
NC
No connection
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.1 2/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
