ESMT
(Preliminary)
F25S04PA
PIN DESCRIPTION
Symbol
Pin Name
Functions
To provide the timing for serial input and
output operations
SCK
Serial Clock
To transfer commands, addresses or data
serially into the device.
SI
Serial Data Input
Data is latched on the rising edge of SCK.
To transfer data serially out of the device.
SO
CE
WP
Serial Data Output
Chip Enable
Data is shifted out on the falling edge of
SCK.
To activate the device when CE is low.
The Write Protect ( WP ) pin is used to
enable/disable BPL bit in the status
register.
Write Protect
To temporality stop serial communication
with SPI flash memory without resetting
the device.
Hold
HOLD
VDD
VSS
Power Supply
Ground
To provide power.
FUNCTIONAL BLOCK DIAGRAM
Flash
Address
Buffers
and
X-Decoder
Latches
Y-Decoder
I/O Butters
Control Logic
and
Data Latches
Serial Interface
CE
SCK
SO
WP
HOLD
SI
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2009
Revision: 0.2
4/34
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
