ESMT
F25L01PA (2D)
INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the F25L01PA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Write Status Register, Sector
Erase, Block Erase, or Chip Erase instructions, the Write Enable
(WREN) instruction must be executed first. The complete list of
the instructions is provided in Table 5. All instructions are
entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read ID, Read Status
Register, Read Electronic Signature instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
synchronized off a high to low transition of CE . Inputs will be
accepted on the rising edge of SCK starting with the most
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
significant bit. CE must be driven low before an instruction is
Table 5: Device Operation Instructions
Bus Cycle 1~3
4
Max.
Freq
Operation
1
2
3
5
6
N
SIN
SOUT
SIN
SOUT SIN SOUT SIN SOUT SIN
SOUT
SIN
SOUT
SIN SOUT
Read
33 MHz 03H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
50 MHz
X
DOUT0
X
DOUT1
X
cont.
Fast Read13
~
0BH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
X
X
X
DOUT0
X
cont.
100 MHz
50 MHz
~
Fast Read Dual
Output11,12
3BH
A23-A16
A15-A8
A7-A0
X
DOUT0~1
cont.
86 MHz
Sector Erase4 (4K Byte)
20H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
D8H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
60H /
-
-
-
-
-
-
-
-
-
-
-
-
Block Erase4, (64K Byte)
Chip Erase
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
C7H
Up to
Page Program (PP)
02H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN0
Hi-Z
DIN1
Hi-Z
256 Hi-Z
bytes
50 MHz
~
Read Status Register
05H Hi-Z
01H Hi-Z
X
DOUT
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(RDSR) 6
Write Status Register
(WRSR)
DIN
-.
-
-
Write Enable (WREN) 9
Write Disable (WRDI)
Deep Power Down (DP)
Release from Deep
Power Down (RDP)
Read Electronic
06H Hi-Z
04H Hi-Z
B9h Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100 MHz
ABH Hi-Z
ABH Hi-Z
9FH Hi-Z
90H Hi-Z
-
X
-
X
-
-
-
-
-
X
-
-
10H
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
Signature (RES) 7
Jedec Read ID
X
8CH
30H
11H
(JEDEC-ID) 8
00H Hi-Z
01H Hi-Z
X
X
8CH
10H
X
X
10H
8CH
-
-
-
-
Read ID (RDID) 10
00H
Hi-Z 00H Hi-Z
Note:
1. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code
2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous
3. One bus cycle is eight clock periods.
4. Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH
Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH
5. To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be
programmed.
6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
7. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
8. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 30H as memory type; third byte 11H as
memory capacity.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.2 8/31
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
