ESMT
F25L01PA (2D)
Table 3: F25L01PA Block Protection Table
Status Register Bit
Protected Memory Area
Protection Level
TB
X
BP2
0
BP1
BP0
0
Block Range
None
Address Range
None
0
0
0
0
0
1
0*
X
1
0
None
None
Upper 1/2
Lower 1/2
All Blocks
0
X
1
Block 1
Block 0
Block 0~1
010000H – 01FFFFH
000000H – 00FFFFH
000000H –00FFFFH
1
X
1
X
X
X
Note: * The combination of Status Register Bit (X100) can’t use Chip Erase instruction.
Block Protection (BP2, BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
WP pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the TB, BPL, BP2, BP1, and BP0 bits. When
the WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”.
BP2, BP1, BP0 bits as long as WP is high or the Block-
Protection-Look (BPL) bit is 0. Chip Erase can only be executed if
Block-Protection bits are all 0. The factory default setting for
Block Protection Bit (BP2 ~ BP0) is 0.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.2
6/31
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
