PBD 3517/1
Phase outputs use a current-sinking
method to drive the windings in a unipolar
way. A common resistor in the center tap
will limit the maximum motor current.
Fast free-wheeling diodes must be
used to protect output transistors from
inductive spikes. Alternative solutions are
shown in figures 21 through 25 on pages
6 - 10.
Series diodes in VMM supply, prevent
VSS voltage from shorting through the VMM
power supply. However, these may be
omitted if no bilevel is used. The VSS pin
must not be connected to a lower voltage
than VMM, but can be left unconnected.
DIR
H
L
INH
HSM
STEP
H
P
OB
L
P
P
P
P
P
P
L
LB
PB1
PB2
PA1
PA2
LA
OA
Figure 16. Full-step mode, forward. 4-step sequence. Gray-code +90° phase shift.
DIR
H
L
INH
HSM
STEP
H
P
Zero outputs
OB
L
P
P
P
P
P
P
L
ØA and ØB, “zero A” and “zero B,” are
open-collector outputs, which go high
when the corresponding phase output is
inhibited by the half-step-mode circuitry. A
pull-up resistor should be used and
connected to a suitable supply voltage (5
kohms for 5V logic). See “Bipolar phase
logic output.”
LB
PB1
PB2
PA1
PA2
LA
OA
Figure 17. Full-step mode, reverse. 4-step sequence. Gray-code -90° phase shift.
DIR
H
L
INH
Interference
HSM
STEP
L
To avoid interference problems, a good
idea is to route separate ground leads to
each power supply, where the only
common point is at the 3517/1’s GND pin.
Decoupling of VSS and VMM will improve
performance. A 5 kohm pull-up resistor at
logic inputs will improve level definitions,
especially when driven by open-collector
outputs.
P
C
OB
P
P
P
P
P
P
P
P
LB
PB1
PB2
PA1
PA2
LA
OA
Figure 18. Half-step mode, forward. 8-step sequence.
DIR
L
L
L
P
Input and Output Signals for
Different Drive Modes
INH
HSM
STEP
The pulse diagrams, figures 16 through
20, show the necessary input signals and
the resulting output signals for each drive
mode.
On the left side are the input and output
signals, the next column shows the state
of each signal at the cursor position
marked “C.”
C
OB
P
P
P
P
P
P
P
P
LB
PB1
PB2
PA1
PA2
LA
OA
Figure 19. Half-step mode, reverse. 8-step sequence.
STEP is shown with a 50% duty cycle,
but can, of course, be with any duty cycle,
as long as pulse time (tp) is within
specifications.
PA and PB are displayed with low level,
showing current sinking.
DIR
L
H
L
INH
HSM
STEP
P
C
OB
P
P
H
H
H
H
P
P
LB
LA and LB are displayed with high level,
showing current sourcing.
PB1
PB2
PA1
PA2
LA
OA
Figure 20. Half-step mode, inhibit.
8
ERICSSON [ ERICSSON ]
