PBD 3517/1
Diagrams
Output Current [A]
10
Output Pulse Width [s]
1
T = +25° C
A
How to use the diagrams:
T = +25° C
A
10-1
8
6
1. What is the maximum motor current
in the application?
10-2
10-3
•
The ambient temperature sets the
maximum allowable power
dissipation in the IC, which
relates to the motor currents and
the duty cycle of the bilevel
function. For PBD 3517/1, without
any measures taken to reduce
the chip temperature via
4
2
0
10-4
10-5
10-6
0.01
0.1
1
10
100
1000
0
0.2
0.4
0.6
0.8
1.0
Ct Capacitance [nF]
heatsinks, the power dissipation
vs. temperature follows the curve
in figure 4.
Output Voltage [V]
Figure 7. Typical IØ vs. VØCE Sat. “Zero
output” saturation.
Figure 8. Typical tOn vs. CT/RT. Output
pulse width vs. capacitance/resistance.
•
•
Figures 9 and 10 give the
relationship between motor
currents and their dissipations.
The sum of these power dissipa-
tions must never exceed the
previously-established value, or
life expectancy will be drastically
shortened.
Output Pulse Width [s]
1
Output Current [A]
(II = 0)
0.5
0.4
T = +25° C
10-1
T = +25° C
A
A
10-2
10-3
When no bilevel or voltage
doubling is utilized, the maximum
motor current can be found
directly in figure 9.
0.3
0.2
0.1
0
10-4
10-5
10-6
2. How to choose timing components.
•
Figure 7 shows the relationship
between CT, RT, and tOn. Care
must be taken to keep the tOn time
short, otherwise the current in the
winding will rise to a value many
times the rated current, causing
an overheated IC or motor.
0
0.2
0.4
0.6
0.8
1.0
0.001 0.01
0.1
1
10
100
Power Dissipation [W]
fs Step frequency [kHz]
Figure 9. Typical tOn vs. fs/dc. Output pulse Figure 10. Typical PDP vs. IP. Power
width vs. step frequency/duty cycle.
dissipation without second-level supply
(includes 2 active outputs = FULL STEP).
3. What is the maximum tOn pulse-width
at a given frequency?
•
Figure 8 shows the relationship
between duty cycle, pulse width,
and step frequency. Check
specifications for the valid
operating area.
Output Current [A]
(Ip = 0)
-0.5
-0.4
Motor Current [mA]
T = +25° C
A
4. Figures 4, 5 and 6 show typical
saturation voltages vs. output current
levels for different output transistors.
Normal
Bilevel
10%
50%
100%
-0.3
Bilevel without
time limit
350
5. Shaded areas represent operating
conditions outside the safe operating
area.
-0.2
-0.1
0
0
0.2
0.4
0.6
0.8
1.0
tON
Time
Power Dissipation [W]
Figure 11. Typical PDI vs. II. Power
dissipation in the bilevel pulse when
Figure 12 . Motor Current 1p.
raising to the II value. One active output.
4
ERICSSON [ ERICSSON ]
