EM48AM1684VTG
256Mb (4M×4Bank×16) Synchronous DRAM
Features
Description
• Fully Synchronous to Positive Clock Edge
• Single 3.3V ±0.3V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
The EM48AM1684VTG is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
4Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
The 256Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are sampled at the Rising Edge of the
System Clock
Available packages: TSOPII 54P 400mil.
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms (7.8us)
Ordering Information
Part No
Organization
Max. Freq
Package
Grade
Pb
EM48AM1684VTG-6F
16M X 16
166MHz @CL3
54pin TSOP(ll) Commercial
54pin TSOP(ll) Commercial
54pin TSOP(II) Commerical
54pin TSOP(ll) Extended
54pin TSOP(ll) Extended
54pin TSOP(II) Extended
Free
EM48AM1684VTG-7F
EM48AM1684VTG-75F
EM48AM1684VTG-6FE
EM48AM1684VTG-7FE
EM48AM1684VTG-75FE
16M X 16
16M X 16
16M X 16
16M X 16
16M X 16
143MHz @CL3
133MHz @CL3
166MHz @CL3
143MHz @CL3
133MHz @CL3
Free
Free
Free
Free
Free
Jun. 2010
2/20
www.eorex.com
EOREX [ EOREX CORPORATION ]
