EM48AM1684VTG
AC Operating Test Conditions
(VDD=3.3V±0.3V, TA=0°C ~70°C)
Item
Conditions
1.4V/1.4V
Output Reference Level
Output Load
See diagram as below
2.4V/0.4V
Input Signal Level
Transition Time of Input Signals
Input Reference Level
2ns
1.4V
AC Operating Test Characteristics
(VDD=3.3V±0.3V, TA=0°C ~70°C)
-6
-7
Symbol
tCK
Parameter
Clock Cycle Time
Units
Min.
6
Max..
Min.
7
Max.
CL=3
CL=2
CL=3
CL=2
-
-
-
-
ns
ns
7.5
-
10
-
5.4
5.4
-
5.4
6
-
tAC
Access Time form CLK
-
-
tCH
tCL
CLK High Level Width
CLK Low Level Width
2
2.5
2.5
2.5
-
ns
ns
2
-
-
CL=3
CL=2
CL=3
CL=2
2.5
-
-
-
tOH
tHZ
Data-out Hold Time
ns
ns
-
-
3
7
-
3
7
-
Data-out High Impedance
Time (Note 5)
-
-
tLZ
tHZ
tIH
Data-out Low Impedance Time
1
-
1
-
ns
ns
Data-out High Impedance Time
Input Hold Time
3
6
-
3
7
-
1
1
ns
tIS
Input Setup Time
1.5
-
1.5
-
ns
tDQZ
tRSC
tSB
tDS
tDH
DQM Data Out Disable Latency
Mode Register Set-up Time
Power Down Mode Entry Time
Data-in Set-up Time
2
-
2
-
CLK
ns
12
0
14
0
6
-
7
-
ns
1.5
1
1.5
1
ns
Data-in Hold Time
-
-
* All voltages referenced to VSS.
Note 5: tHZ defines the time at which the output achieve the open circuit condition and is not referenced to
output voltage levels.
Jun. 2010
9/20
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EOREX [ EOREX CORPORATION ]
