EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
3)
VTM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
2)
R1
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL
2)
R2
CL1)
CL1) = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R1=3070W,
R2=3150W
3. VTM=2.8V
READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
55ns
70ns
Symbol
Parameter
Read cycle time
Unit
Min
Max
Min
Max
tRC
tAA
55
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
-
55
55
25
30
-
-
-
-
70
70
35
35
-
Chip select to output
tco
Output enable to valid output
UB, LB acess time
tOE
tBA
Chip select to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
tLZ
10
5
10
5
tBLZ
tOLZ
tHZ
-
-
5
-
5
-
0
20
20
20
-
0
25
25
25
-
tBHZ
tOHZ
tOH
0
0
0
0
10
10
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
55ns
70ns
Unit
Symbol
Parameter
Write cycle time
Min
Max
Min
Max
tWC
tCW
tAs
55
-
70
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
-
-
-
Address valid to end of write
UB, LB valid to end of write
Write pulse width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
45
45
40
0
-
60
60
50
0
-
-
-
-
-
Write recovery time
-
-
Write to ouput high-Z
0
25
0
30
Data to write time overlap
Data hold from write time
End write to output low-Z
25
0
30
0
-
-
-
-
tOW
5
5
5
EMLSI [ Emerging Memory & Logic Solutions Inc ]
