EM78P447S
OTP ROM
4. FUNCTION DESCRIPTION
OSCI OSCO
/RESET
TCC /INT
W DT Tim er
STACK 1
STACK 2
STACK 3
STACK 4
STACK 5
P C
Oscillator/Tim ing
Control
Prescale
r
ROM
W DT
Tim-eout
Interrupt
Control
Instruction
Register
R1(TCC)
ALU
ACC
Instruction
Decoder
Sleep
&
RAM
R4
R3
W ake
Control
DATA & CONTROL BUS
IOC6
IOC5
R5
IOC7
R7
R6
PPPPPPPP
66666666
01234567
PPPPPPPP
55555555
01234567
PPPPPPPP
77777777
01234567
Fig. 2 Functional Block Diagram
4.1 Operational Registers
1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to act as an indirect addressing
pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select
Register (R4).
2. R1 (Time Clock /Counter)
• Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or by
the instruction cycle clock.
• Writable and readable as any other registers.
• Defined by resetting PAB (CONT-3).
• The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
• The contents of the prescaler counter will be cleared only when TCC register is written a value.
This specification is subject to change without prior notice.
8
06.25.2003 (V1.1)
ELAN [ ELAN MICROELECTRONICS CORP ]
