EM78910/910A
8-bit Micro-controller
* Bit 3~0 (PS3~PS0) : Program page selection bits
Program page select bits
PS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Program memory page (Address)
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
Page 9
Page 10
Page 11
Page 12
Page 13
Page 14
Page 15
User can use PAGE instruction to change page and maintain program page by user. Otherwise, user can use
far jump (FJMP) or far call (FCALL) instructions to program user's code. The program page is maintained
by EMC's complier. It will change user's program by inserting instructions within program.
* Bit 7~4 (R57 ~ R54) : 4-bit I/O register for PORT57~PORT53 I/O
7. R6,R7 and R9 (I/O registers for PORT6, PORT7 and PORT9)
* R6, R7 and R9 are four 8-bit I/O registers for PORT6, PORT7 and PORT9.
8. R8 (General-purpose)
* R8 is a general-purpose register.
9. RA (CPU mode selection, Low battery detection, FSK power and output status, Ring detection output)
7
6
5
4
3
2
1
0
IDLE ENPLL /LPD /LOW_BAT /FSKPWR DATA
/CD
/RD
* Bit 0 (/RD) : (Read Only) Ring signal detection output, 0/1 ! Ring signal valid/Ring signal invalid
* Bit 1 (/CD) : (Read Only) FSK carrier signal detection output, 0/1 ! Carrier signal valid/Carrier signal
invalid
* Bit 2 (DATA) : (Read Only)(FSK demodulator output signal)
Fsk data transmitted in a baud rate 1200 Hz.
* Bit 3 (/FSKPWR) : Power up/down FSK block, 1/0 ! power up FSK block/power down FSK block
When FSK is powered on, PLL is also enabled regardless of RA bit 6 (ENPLL). When FSK is
powered off, PLL status is depended on RA bit 6 (ENPLL) setting.
The relation between Bit 0 to Bit 3 is shown in Fig.6.
__________________________________________________________________________________________________________________________________________________________________
* This specification are subject to be changed without notice.
~ ~
2001/01/12
7
ELAN [ ELAN MICROELECTRONICS CORP ]
