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EM78910 参数 Datasheet PDF下载

EM78910图片预览
型号: EM78910
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8-BIT MICRO-CONTROLLER]
分类和应用: 微控制器
文件页数/大小: 30 页 / 299 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78910/910A  
8-bit Micro-controller  
ADDRESS  
REGISTER  
CONTROL REGISTER  
(PAGE0)  
CONTROL REGISTER  
(PAGE1)  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
R0  
R1(TCC)  
R2(PC)  
R3(STATUS)  
page0  
R4(RSR)  
R5(PORT5,ROM PAGE)  
R6(PORT6)  
IOC5  
IOC6  
R7(PORT7)  
IOC7  
R8(general purpose register)  
R9(PORT9)  
IOC8 = 00000000  
IOC9  
page1  
RA(CLK,FSK)  
RB(DTMF)  
IOCA  
IOCB = 00000000  
IOCC = 00000000  
IOCD(PULL HIGH)  
IOCE = 00000000  
IOCF(INT CONTROL)  
IOCB(COUNTER1)  
IOCC(COUNTER2)  
IOCD(R-OPTION)  
RC(1.0K RAM ADDRESS)  
RD(1.0K RAM DATA)  
RE(WDT)  
RF(INT FLAG)  
10  
:
16 X8  
COMMON  
REGISTER  
RC(ADDRESS) RD(DATA)  
1F  
0
BANK0 ~BANK3  
32X8 ~32X8  
REGISTER  
20  
:
BANK3 BANK4  
BANK1 BANK2  
256X8 256X8  
:
256X8 256X8  
3F  
255  
Fig.5 Data memory configuration  
4. R3 (CW and SDT output, CPU power control, Register page selection, Status flags)  
7
6
5
4
3
2
1
0
CAS PAGE /SDT  
* Bit 0 (C) : Carry flag  
T
P
Z
DC  
C
* Bit 1 (DC) : Auxiliary carry flag  
* Bit 2 (Z) : Zero flag  
* Bit 3 (P) : Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP"  
command.  
* Bit 4 (T) : Time-out bit. Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0  
by WDT timeout.  
EVENT  
T
P
REMARK  
WDT wake up from sleep mode  
WDT time out (not sleep mode  
/RESET wake up from sleep  
power up  
0
0
1
1
x
0
1
0
1
Low pulse on /RESET  
X
X : don't care  
* Bit 5 (/SDT) : (Read Only) Stuttered dial tone signal detection output, 0/1 => SDT signal valid/SDT signal  
invalid  
* Bit 6 (PAGE) : Change IOCB ~ IOCE to another page, 0/1 ! PAGE0/PAGE1  
* Bit 7 (CAS) : (Read Only) Call waiting signal detection output, 0/1 ! CW signal valid/signal invalid  
5. R4 (RAM address selection)  
* Bits 0 ~ 5 are used to select up to 64 registers in the indirect addressing mode.  
* Bits 6 ~ 7 determine which bank is activated among the 4 banks.  
* See the configuration of the data memory in Fig.5.  
6. R5 (PORT5(7:4) I/O registers, Program page selection)  
7
6
5
4
3
2
1
0
R57  
R56  
R55  
R54  
PS3  
PS2  
PS1  
PS0  
__________________________________________________________________________________________________________________________________________________________________  
* This specification are subject to be changed without notice.  
~ ~  
2001/01/12  
6