EM73P461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
** FHTC=[(XIN/2X)/(100H-HT)]/2, HT=0~255
** Example : LXIN=32K Hz, HIPS=01, HT=11110000B=0F0H.
FHTC=[(32K Hz/22)/(100H-0f0H)]/2=256 Hz.
LDIA
#1111B
P11
#0000B
P10
#1001B
P31
OUTA
LDIA
OUTA
LDIA
OUTA
The value of 8-bit binary up counter can be presetted by P10 and P11. The value of registers can loaded into
the HTC when the counter starts counting or occurs overflow. If user write value to the registers before the
next overflow occurs, the preset value can be changed.
The preset value will be changed when users output the different data to P10 and P11.
The count value of HTC can be read from P10 and P11. The value is unstable when user read the value during
counting. Thus, user must disable the counter before reading the value.
The P4.0/SOUND and SOUND pins will output the squre wave in the melody mode. When the CPU is not
in the melody mode, the P4.0/SOUND is high and SOUND is low.
The P4.1/RGH pin will be the input pin in the pulse width measurement mode. User must output high to P4.1/
TRGH and then it can be the HTC external input pin. When the HTC is disabled, the P4.1 pin is a normal I/
O pin.
INTERRUPT FUNCTION
There are 6 interrupt sources, 2 external interrupt sources, 4 internal interrupt sources. Multiple
interrupts are admitted according the priority.
Type
Interrupt source
Priority Interrupt
Interrupt
Program ROM
Latch Enable condition entry address
External Externalinterrupt(INT0)
1
2
3
4
5
6
IL5
IL4
IL3
IL2
IL1
IL0
EI=1
002H
004H
006H
008H
00AH
00CH
Internal High speed timer overflow interrupt (HTCI)
Internal TimerAoverflowinterrupt(TRGA)
Internal TimerBoverflowinterrupt(TRGB)
Internal Time base interrupt(TBI)
EI=1,MASK3=1
EI=1,MASK2=1
EI=1,MASK1=1
External Externalinterrupt(INT1)
EI=1,MASK0=1
INTERRUPT STRUCTURE
MASK0 MASK1 MASK1 MASK2 MASK3
INT1 TRGA HTCI
INT0
r5
TBI TRGB
r1 r2
r0 r3 r4
Reset by system reset and program
instruction
IL2
IL3
IL4
IL0
IL1
IL5
Priority checker
Reset by system reset and program
instruction
Set by program instruction
Entry address generator
Interrupt entry address
EI
Interrupt request
* This specification are subject to be changed without notice.
12.27.2001
22