EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
(8) Bit manipulation
Mnemonic Object code ( binary ) Operation description
Byte
Cycle
Flag
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
S
1
1
1
1
1
1
1
1
*
*
*
*
*
*
*
CLM
CLP
CLPL
CLR
SEM
SEP
b
1111 00bb
RAM[HL]b←0
PORT[p]b←0
PORT[LR3-2+4]LR1-0←0
RAM[y]b←0
RAM[HL]b←1
PORT[p]b←1
PORT[LR3-2+4]LRl-0←1
RAM[y]b←1
SF←RAM[y]b'
SF←Accb'
SF←RAM[HL]b'
SF←PORT[p]b'
SF←PORT[LR3-2+4]LR1-0'
SF←RAM[y]b
1
2
1
2
1
2
1
2
2
1
1
2
1
2
2
1
2
2
2
1
2
2
2
2
1
1
2
2
2
2
p,b 0110 1101 11bb pppp
0110 0000
y,b 0110 1100 11bb yyyy
b
1111 01bb
p,b 0110 1101 01bb pppp
0110 0010
SEPL
SET
TF
y,b 0110 1100 01bb yyyy
y,b 0110 1100 00bb yyyy
TFA
TFM
TFP
b
1111 10bb
1111 11bb
b
p,b 0110 1101 00bb pppp
0110 0001
TFPL
TT
y,b 0110 1100 10bb yyyy
p,b 0110 1101 10bb pppp
TTP
SF←PORT[p]b
(9) Subroutine
Mnemonic
LCALL a
Object code ( binary ) Operation description
Byte
Cycle
Flag
C
Z
S
0100 0aaa aaaa aaaa
1110 nnnn
STACK[SP]←PC,
SP←SP -1, PC←a
STACK[SP]←PC,
2
1
2
2
-
-
-
SCALL a
-
-
-
-
-
-
SP←SP - 1, PC←a,
a = 8n +6 (n=1~15),0086h (n =0)
RET
0100 1111
SP←SP + 1, PC←STACK[SP]
1
2
(10) Input/output
Mnemonic
Object code ( binary ) Operation description
Byte
Cycle
Flag
C
-
Z
Z
-
S
INA
INM
p
p
0110 1111 0100 pppp
0110 1111 1100 pppp
Acc←PORT[p]
RAM[HL]←PORT[p]
PORT[p]←k
PORT[p]←Acc
PORT[p]←RAM[HL]
2
2
2
2
2
2
2
2
2
2
Z'
Z'
1
-
OUT #k,p 0100 1010 kkkk pppp
OUTA p
OUTM p
-
-
0110 1111 000p pppp
0110 1111 100p pppp
-
-
1
-
-
1
(11) Flag manipulation
Mnemonic
Object code ( binary ) Operation description
Byte
Cycle
Flag
C
-
Z
-
S
1
1
*
CGF
SGF
0101 0111
0101 0101
0101 0011
GF←0
GF←1
SF←CF', CF←0
1
1
1
1
1
1
-
-
TFCFC
0
-
* This specification are subject to be changed without notice.
7.20.1999 28
ELAN [ ELAN MICROELECTRONICS CORP ]
