EM39LV088
8M Bits (1Mx8) Flash Memory
SPECIFICATION
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a
write cycle.
V
DD Power Up/Down Detection: The Write operation is inhibited when VDD is less than
1.5V.
Write Inhibit Mode: Forcing OE# Low, CE# High, or WE# High will inhibit the
Write operation. This prevents inadvertent write during
power-up or power-down.
Software Data Protection (SDP)
The EM39LV088 provides the JEDEC approved Software Data Protection (SDP) scheme for
Program and Erase operations. Any Program operation requires the inclusion of the
three-byte sequence. The three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent Write operations, especially during
the system power-up or power-down transition. Any Erase operation requires the inclusion of
six-byte sequence. See Table 3 for the specific software command codes. During SDP
command sequence, invalid commands will abort the device to Read mode within TRC. The
contents of DQ7-DQ0 can be VIL or VIH, but no other value, during any SDP command
sequence.
This specification is subject to change without further notice. (04.09.2004 V1.0)
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ELAN [ ELAN MICROELECTRONICS CORP ]
