EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
Memory Organization
The memory is organized as:
ꢀ
ꢀ
ꢀ
131,072 Bytes (8 bits per byte)
4 Blocks (256K bits or 32,768 bytes per block)
512 Pages (256 bytes per page)
Each page can be individually programmed (bits are programmed from “1” to “0”). The
device is Block or Chip Erasable (bits are erased from “0” to “1”), but not Page Erasable.
Block
Address Range
3
2
1
0
18000h
1FFFFh
17FFFh
0FFFFh
07FFFh
10000h
08000h
00000h
Table 2: Memory Organization
Hold#
W #
Control Logic
S#
C
D
Q
I/O Buffer and Data Latches
256 Byte Data Buffer
Status
Register
Address Register
and Counter
1FFFFh
Block3
18000h
Block2
10000h
Size of the
read-only
memory area
Block1
08000h
Block0
00000h
000FFh
256 Bytes (Page Size)
Y-Decoder
Figure 2: SPI Modes Supported
This specification is subject to change without further notice. (11.08.2004 V1.0)
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ELAN [ ELAN MICROELECTRONICS CORP ]
