EBJ21UE8BFU0
Serial PD Matrix
-DJ
-GN
-GL
Byte No. Function described
Hex Comments
Hex Comments
Hex Comments
Number of serial PD bytes written/
0
92h 176/256/0-116
92h 176/256/0-116
92h 176/256/0-116
SPD device size/CRC coverage
SPD revision
1
2
3
4
10h Rev.1.0
10h Rev.1.0
10h Rev.1.0
Key byte/DRAM device type
Key byte/module type
0Bh DDR3 SDRAM
03h SO-DIMM
0Bh DDR3 SDRAM
03h SO-DIMM
0Bh DDR3 SDRAM
03h SO-DIMM
SDRAM density and banks
02h 1G bits, 8 banks
02h 1G bits, 8 banks
02h 1G bits, 8 banks
14 rows,
10 columns
14 rows,
10 columns
14 rows,
10 columns
5
SDRAM addressing
11h
11h
11h
6
7
8
Module nominal voltage, VDD
Module organization
00h 1.5V
00h 1.5V
00h 1.5V
09h 2 ranks/×8 bits
03h 64 bits/non-ECC
09h 2 ranks/×8 bits
03h 64 bits/non-ECC
09h 2 ranks/×8 bits
03h 64 bits/non-ECC
Module memory bus width
Fine timebase (FTB)
dividend/divisor
9
52h 5/2
52h 5/2
52h 5/2
10
11
Medium timebase (MTB) dividend
01h
08h
1
8
01h
08h
1
8
01h
08h
1
8
Medium timebase (MTB) divisor
SDRAM minimum cycle time
(tCK (min.))
Reserved
12
0Ch 1.5ns
00h
0Ah 1.25ns
00h
FEh 5, 6, 7, 8, 9, 10, 11 FEh 5, 6, 7, 8, 9, 10, 11
00h 00h
0Ah 1.25ns
13
14
—
—
00h
—
SDRAM CAS latencies supported, LSB7Eh 5, 6, 7, 8, 9, 10
SDRAM CAS latencies supported,
MSB
SDRAM minimum CAS latencies
time (tAA (min.))
SDRAM minimum write recovery
time (tWR (min.))
SDRAM minimum /RAS to /CAS
delay (tRCD (min.))
SDRAM minimum row active to row
active delay (tRRD (min.))
SDRAM minimum row precharge
time (tRP (min.))
SDRAM upper nibbles for tRAS and
tRC
SDRAM minimum active to
precharge time (tRAS (min.)), LSB
SDRAM minimum active to active
/auto-refresh time (tRC (min.)), LSB
SDRAM minimum refresh recovery
time delay (tRFC (min.)), LSB
SDRAM minimum refresh recovery
time delay (tRFC (min.)), MSB
SDRAM minimum internal write to
read command delay (tWTR (min.))
15
16
17
18
19
20
21
22
23
24
25
26
00h
—
—
—
69h 13.125ns
78h 15ns
69h 13.125ns
78h 15ns
64h 12.5ns
78h 15ns
64h 12.5ns
30h 6ns
69h 13.125ns
30h 6ns
69h 13.125ns
30h 6ns
69h 13.125ns
69h 13.125ns
64h 12.5ns
11h
—
11h
—
11h —
20h 36ns
18h 35ns
18h 35ns
7Ch 47.5ns
70h 110ns
03h 110ns
3Ch 7.5ns
89h 49.125ns
70h 110ns
03h 110ns
3Ch 7.5ns
81h 48.125ns
70h 110ns
03h 110ns
3Ch 7.5ns
SDRAM minimum internal read to
precharge command delay
(tRTP (min.))
27
3Ch 7.5ns
3Ch 7.5ns
3Ch 7.5ns
28
29
30
31
Upper nibble for tFAW
Minimum four activate window delay
time (tFAW (min.))
00h 30ns
F0h 30ns
00h 30ns
00h 30ns
F0h 30ns
F0h 30ns
SDRAM optional features
83h DLL-off, RZQ/6, 7
PASR/2X refresh at
83h DLL-off, RZQ/6, 7
83h DLL-off, RZQ/6, 7
PASR/2X refresh at
+85ºC to +95ºC
PASR/2X refresh at
+85ºC to +95ºC
SDRAM thermal and refresh options 81h
81h
81h
+85ºC to +95ºC
Data Sheet E1642E30 (Ver. 3.0)
5
ELPIDA [ ELPIDA MEMORY ]
