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EBJ21UE8BBF0-AE-F 参数 Datasheet PDF下载

EBJ21UE8BBF0-AE-F图片预览
型号: EBJ21UE8BBF0-AE-F
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM Module, 256MX64, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 18 页 / 194 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBJ21UE8BBF0-AE-F的Datasheet PDF文件第3页浏览型号EBJ21UE8BBF0-AE-F的Datasheet PDF文件第4页浏览型号EBJ21UE8BBF0-AE-F的Datasheet PDF文件第5页浏览型号EBJ21UE8BBF0-AE-F的Datasheet PDF文件第6页浏览型号EBJ21UE8BBF0-AE-F的Datasheet PDF文件第8页浏览型号EBJ21UE8BBF0-AE-F的Datasheet PDF文件第9页浏览型号EBJ21UE8BBF0-AE-F的Datasheet PDF文件第10页浏览型号EBJ21UE8BBF0-AE-F的Datasheet PDF文件第11页  
EBJ21UE8BBF0  
Hex  
Byte No. Function described  
SDRAM minimum active to active /auto-  
refresh time (tRC), LSB  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments  
23  
1
0
0
0
1
1
0
0
8CH 49.5ns  
-DJ  
-AE  
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
0
95H  
50.625ns  
-8C  
A4H 52.5ns  
SDRAM minimum refresh recovery time  
delay (tRFC), LSB  
24  
25  
26  
27  
28  
0
0
0
0
1
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
70H  
03H  
110ns  
110ns  
SDRAM minimum refresh recovery time  
delay (tRFC), MSB  
0
SDRAM minimum internal write to read  
command delay (tWTR)  
1
1
3CH 7.5ns  
3CH 7.5ns  
SDRAM minimum internal read to  
precharge command delay (tRTP)  
Upper nibble for tFAW  
-DJ  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
00H  
01H  
-AE, -8C  
0
Minimum four activate window delay time  
29  
(tFAW)  
-DJ  
1
1
1
1
0
0
0
0
F0H  
30ns  
-AE  
0
0
1
0
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
2CH 37.5ns  
-8C  
40H  
83H  
40ns  
30  
31  
SDRAM output drivers supported  
DLL-off/RZQ/6, 7  
PASR/ 2X refresh rate  
at +85°C to +95°C  
SDRAM refresh options  
1
0
0
0
0
0
0
1
81H  
32  
33  
Module thermal sensor  
SDRAM device type  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
1
1
00H  
00H  
00H  
0FH  
11H  
01H  
Not incorporated  
Standard  
34 to 59 Reserved  
60  
61  
62  
Module nominal height  
29 < height 30mm  
Module maximum thickness  
Reference raw card used  
Raw Card B  
Mirrored  
Address mapping from edge connecter to  
DRAM  
63  
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
1
0
0
0
01H  
00H  
02H  
64 to  
116  
Module specific section  
Module ID: manufacturer’s JEDEC ID  
code, LSB  
117  
118  
Elpida Memory  
Module ID: manufacturer’s JEDEC ID  
code, MSB  
FEH Elpida Memory  
119  
120  
121  
Module ID: manufacturing location  
Module ID: manufacturing date  
Module ID: manufacturing date  
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
××  
××  
××  
Year code (BCD)  
Week code (BCD)  
122 to  
125  
Module ID: module serial number  
×
×
×
×
×
×
×
×
××  
Cyclical redundancy code (CRC)  
-DJ  
126  
1
1
0
1
1
1
0
0
DCH  
-AE  
-8C  
1
0
1
1
1
1
0
1
1
0
0
0
0
0
1
1
E9H  
71H  
Data Sheet E1409E30 (Ver. 3.0)  
7