EBJ21UE8BBF0
Serial PD Matrix
Hex
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments
Number of serial PD bytes written/SPD
device size/CRC coverage
0
1
0
0
1
0
0
1
0
92H
10H
176/256/0-116
Revision 1.0
1
SPD revision
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
0
1
0
0
1
0
1
1
0
1
0
2
Key byte/DRAM device type
Key byte/module type
0BH DDR3 SDRAM
3
02H
02H
11H
00H
09H
03H
52H
01H
08H
Unbuffered
4
SDRAM density and banks
SDRAM addressing
1G bits, 8 banks
5
14 rows, 10 columns
6
Module nominal voltage, VDD
Module organization
1.5V
7
2 ranks/×8 bits
8
Module memory bus width
Fine timebase (FTB) dividend/divisor
Medium timebase (MTB) dividend
Medium timebase (MTB) divisor
64 bits/non-ECC
9
5/2
1
10
11
8
SDRAM minimum cycle time
12
(tCK (min.))
-DJ
0
0
0
0
1
1
0
0
0CH 1.5ns
-AE
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
0
1
0
0
0FH
14H
00H
1.875ns
-8C
2.5ns
—
13
14
Reserved
SDRAM /CAS latencies supported, LSB
-DJ
0
0
1
1
1
1
0
0
3CH CL = 6, 7, 8, 9
1CH CL = 6, 7, 8
-AE
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
0
0
0
0
0
-8C
04H
00H
CL = 6
—
15
16
SDRAM /CAS latencies supported, MSB
SDRAM minimum /CAS latencies time
(tAA (min.))
-DJ, -AE
0
1
1
0
1
0
0
1
69H
13.125ns
-8C
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
78H
78H
15ns
15ns
17
18
SDRAM write recovery time (tWR)
SDRAM minimum /RAS to /CAS delay
(tRCD)
-DJ, -AE
0
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
69H
78H
30H
13.125ns
15ns
-8C
SDRAM minimum row active to row active
delay (tRRD)
-DJ
19
20
6ns
-AE
-8C
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
0
3CH 7.5ns
50H
10ns
SDRAM minimum row precharge time
(tRP)
-DJ, -AE
0
1
1
0
1
0
0
1
69H
13.125ns
15ns
-8C
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
1
78H
11H
21
22
SDRAM upper nibbles for tRAS and tRC
SDRAM minimum active to precharge time
(tRAS), LSB
-DJ
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
20H
36ns
-AE, -8C
2CH 37.5ns
Data Sheet E1409E30 (Ver. 3.0)
6
ELPIDA [ ELPIDA MEMORY ]
