EBJ21UE8BAU0
Block Diagram
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
/RESET
/RESET:SDRAMs (D0 to D15)
VTT
VDDSPD
VREFCA
Serial PD
SPD
V2
V4
V1V9
V5
V8
V6
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SCL
SA0
SA1
SCL
A0
SDA
SDA
D1
V3
D8
D3
D7
D14
V7
VREFDQ
VDD
U0
A1
A2
D12
D13
D2
VSS
SDRAMs (D0 to D15), SPD
WP
Notes :
1. DQ wiring may be changed within a byte.
2. DQ, DQS, /DQS, ODT, DM, CKE, /CS relationships
must be maintained as shown.
V5
V6
V8
V4
V2
D10
D11
D0
D4
D5
VTT
V3
D9
V7
D6
* D0 to D15: 1G bits DDR3 SDRAM
Address, BA: A0 to A13, BA0 to BA2
Command: /RAS, /CAS, /WE
U1: 256 bytes EEPROM
Rs1: 15
V1
D15
V9
Address and Control lines
Rs2: 36
Rs3: 30
Rs4: 240
Data Sheet E1244E40 (Ver. 4.0)
9
ELPIDA [ ELPIDA MEMORY ]
