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EBJ11RD8BAFA-8A-E 参数 Datasheet PDF下载

EBJ11RD8BAFA-8A-E图片预览
型号: EBJ11RD8BAFA-8A-E
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM Module, 128MX72, 0.4ns, CMOS, ROHS COMPLIANT, DIMM-240]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 21 页 / 226 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBJ11RD8BAFA  
Pin Description  
Pin name  
Function  
Address input  
Row address  
Column address  
A0 to A15  
A0 to A12  
A0 to A9  
A10 (AP)  
Auto precharge  
Burst chop  
A12 (/BC)  
BA0, BA1, BA2  
Bank select address  
Data input/output  
DQ0 to DQ63  
CB0 to CB7  
Check bit (Data input/output)  
Row address strobe command  
Column address strobe command  
Write enable  
/RAS  
/CAS  
/WE  
/CS0, /CS1  
Chip select  
CKE0, CKE1  
Clock enable  
CK0  
Clock input  
/CK0  
Differential clock input  
Input and output data strobe  
Termination data strobe  
Clock input for serial PD  
Data input/output for serial PD  
Serial address input  
DQS0 to DQS8, /DQS0 to /DQS8  
TDQS9 to TDQS17, /TDQS9 to /TDQS17  
SCL  
SDA  
SA0, SA1, SA2  
VDD  
Power for internal circuit  
Power for serial EEPROM  
Reference voltage for CA  
Reference voltage for DQ  
Ground  
VDDSPD  
VREFCA  
VREFDQ  
VSS  
VTT  
Termination Voltage  
/RESET  
ODT0, ODT1  
Par_In  
Set DRAM to known state  
ODT control  
Parity bit for the Address and Control bus  
Parity error found on the Address and Control bus  
/Err_Out  
/Event  
Reserved for optional hardware temperature sensing  
No connection  
NC  
Preliminary Data Sheet E1189E20 (Ver. 2.0)  
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