EBE82AF4A1RA
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
128 bytes
256 bytes
Total number of bytes in serial PD
device
2
3
4
5
6
7
8
Memory type
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
1
0
1
0
0
0
1
0
0
0
0
1
0
1
1
1
0
0
0
0
0
1
1
0
0
1
08H
0EH
0BH
73H
48H
00H
05H
DDR2 SDRAM
Number of row address
Number of column address
Number of DIMM ranks
Module data width
14
11
DDP/4 ranks
72
Module data width continuation
Voltage interface level of this assembly
0
SSTL 1.8V
DDR SDRAM cycle time, CL = 5
-6E
9
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
0
0
0
1
1
0
1
0
0
0
0
1
0
1
1
0
0
30H
3DH
45H
50H
06H
3.0ns*1
3.75ns*1
0.45ns*1
0.5ns*1
-5C
SDRAM access from clock (tAC)
-6E
10
-5C
ECC, Address/
command Parity
11
DIMM configuration type
12
13
14
15
Refresh rate/type
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
82H
04H
04H
00H
7.8μs
× 4
× 4
0
Primary SDRAM width
Error checking SDRAM width
Reserved
SDRAM device attributes:
Burst length supported
16
17
18
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0CH
08H
38H
4,8
SDRAM device attributes: Number of
banks on SDRAM device
8
SDRAM device attributes:
/CAS latency
3, 4, 5
19
20
21
DIMM Mechanical Characteristics
DIMM type information
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
02H
01H
00H
6.00mm max.
Registered
Normal
SDRAM module attributes
Weak Driver
50Ω ODT
Support
22
SDRAM device attributes: General
Minimum clock cycle time at CL = 4
0
0
0
0
0
0
1
1
03H
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
1
0
1
1
0
1
1
1
0
1
1
1
0
0
1
0
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
0
3DH
50H
50H
60H
3CH
1EH
3CH
2DH
02H
3.75ns*1
0.5ns*1
5.0ns*1
0.6ns*1
15ns
Maximum data access time (tAC) from
clock at CL = 4
Minimum clock cycle time at CL = 3
Maximum data access time (tAC) from
clock at CL = 3
Minimum row precharge time (tRP)
Minimum row active to row active delay
(tRRD)
7.5ns
Minimum /RAS to /CAS delay (tRCD)
15ns
Minimum active to precharge time
(tRAS)
45ns
Module rank density
2GB
Preliminary Data Sheet E1166E10 (Ver. 1.0)
5
ELPIDA [ ELPIDA MEMORY ]
