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EBE41AF4A1QB-8G-E 参数 Datasheet PDF下载

EBE41AF4A1QB-8G-E图片预览
型号: EBE41AF4A1QB-8G-E
PDF下载: 下载PDF文件 查看货源
内容描述: 4GB的VLP注册DDR2 SDRAM DIMM [4GB VLP Registered DDR2 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 27 页 / 231 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE41AF4A1QB-8G-E的Datasheet PDF文件第2页浏览型号EBE41AF4A1QB-8G-E的Datasheet PDF文件第3页浏览型号EBE41AF4A1QB-8G-E的Datasheet PDF文件第4页浏览型号EBE41AF4A1QB-8G-E的Datasheet PDF文件第5页浏览型号EBE41AF4A1QB-8G-E的Datasheet PDF文件第7页浏览型号EBE41AF4A1QB-8G-E的Datasheet PDF文件第8页浏览型号EBE41AF4A1QB-8G-E的Datasheet PDF文件第9页浏览型号EBE41AF4A1QB-8G-E的Datasheet PDF文件第10页  
EBE41AF4A1QB  
Byte No. Function described  
Maximum data access time (tAC) from  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments  
clock at CL = X 2  
0
1
0
1
0
0
0
0
50H  
0.5ns*1  
26  
-8G (CL = 4)  
-6E (CL = 3)  
0
0
1
0
1
1
0
1
0
1
0
1
0
0
0
0
60H  
3CH  
0.6ns*1  
15ns  
27  
28  
29  
30  
31  
Minimum row precharge time (tRP)  
Minimum row active to row active delay  
(tRRD)  
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
1
1
0
1
1
1
0
1
0
0
1
0
0
1
0
1EH  
3CH  
2DH  
02H  
7.5ns  
15ns  
45ns  
2GB  
Minimum /RAS to /CAS delay (tRCD)  
Minimum active to precharge time  
(tRAS)  
Module rank density  
Address and command setup time  
before clock (tIS)  
-8G  
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
1
1
0
0
1
0
1
17H  
20H  
25H  
0.17ns*1  
0.20ns*1  
0.25ns*1  
32  
33  
-6E  
Address and command hold time after  
clock (tIH)  
-8G  
-6E  
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
1
1
1
0
0
27H  
05H  
10H  
12H  
0.27ns*1  
0.05ns*1  
0.10ns*1  
0.12ns*1  
Data input setup time before clock (tDS)  
-8G  
34  
35  
-6E  
Data input hold time after clock (tDH)  
-8G  
-6E  
0
0
0
0
0
1
1
1
0
1
1
1
1
0
1
0
17H  
3CH  
0.17ns*1  
15ns*1  
36  
37  
Write recovery time (tWR)  
Internal write to read command delay  
(tWTR)  
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1EH  
1EH  
7.5ns*1  
Internal read to precharge command  
delay (tRTP)  
38  
7.5ns*1  
TBD  
39  
40  
41  
Memory analysis probe characteristics  
Extension of Byte 41 and 42  
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
1
1
0
1
0
0
0
0
00H  
06H  
3CH  
Active command period (tRC)  
60ns*1  
Auto refresh to active/  
Auto refresh command cycle (tRFC)  
42  
43  
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
1
0
0
0
0
7FH  
80H  
14H  
18H  
1EH  
127.5ns*1  
8ns*1  
SDRAM tCK cycle max. (tCK max.)  
Dout to DQS skew  
-8G  
0.20ns*1  
0.24ns*1  
0.30ns*1  
44  
45  
-6E  
Data hold skew (tQHS)  
-8G  
-6E  
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
0
22H  
0FH  
00H  
12H  
0.34ns*1  
46  
PLL relock time  
15µs  
47 to 61  
62  
SPD Revision  
Rev. 1.2  
Checksum for bytes 0 to 62  
-8G  
63  
1
0
1
0
1
1
0
0
ACH  
-6E  
1
0
1
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
0
1
0
0
E2H  
7FH  
FEH  
00H  
64 to 65 Manufacturer’s JEDEC ID code  
66 Manufacturer’s JEDEC ID code  
Continuation code  
Elpida Memory  
67 to 71 Manufacturer’s JEDEC ID code  
Preliminary Data Sheet E1246E10 (Ver. 1.0)  
6