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EBE25UD6ABSA 参数 Datasheet PDF下载

EBE25UD6ABSA图片预览
型号: EBE25UD6ABSA
PDF下载: 下载PDF文件 查看货源
内容描述: 256MB DDR2 SDRAM SO- DIMM [256MB DDR2 SDRAM SO-DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 21 页 / 235 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE25UD6ABSA  
Serial PD Matrix  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value  
Comments  
128 bytes  
Number of bytes utilized by module  
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H  
08H  
manufacturer  
Total number of bytes in serial PD  
256 bytes  
device  
2
3
4
5
6
7
8
Memory type  
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
08H  
0DH  
0AH  
60H  
40H  
00H  
05H  
DDR2 SDRAM  
Number of row address  
Number of column address  
Number of DIMM ranks  
Module data width  
13  
10  
1
64  
Module data width continuation  
0
Voltage interface level of this assembly 0  
SSTL 1.8V  
DDR SDRAM cycle time, CL = 5  
9
0
0
1
1
1
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
0
0
3DH  
50H  
50H  
3.75ns*1  
5.0ns*1  
0.5ns*1  
-5C  
-4A  
0
0
SDRAM access from clock (tAC)  
-5C  
10  
-4A  
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
60H  
00H  
82H  
10H  
00H  
00H  
0.6ns*1  
None.  
7.8µs  
× 16  
11  
12  
13  
14  
15  
DIMM configuration type  
Refresh rate/type  
Primary SDRAM width  
Error checking SDRAM width  
Reserved  
None.  
0
SDRAM device attributes:  
16  
17  
18  
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0CH  
04H  
38H  
4,8  
Burst length supported  
SDRAM device attributes: Number of  
banks on SDRAM device  
SDRAM device attributes:  
/CAS latency  
4
3, 4, 5  
19  
20  
21  
22  
Reserved  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
00H  
04H  
00H  
01H  
0
DIMM type information  
SDRAM module attributes  
SDRAM device attributes: General  
SO-DIMM  
Normal  
Weak driver  
Minimum clock cycle time at CL = 4  
-5C  
-4A  
23  
0
0
0
1
1
0
1
1
1
0
1
0
0
0
1
0
3DH  
50H  
3.75ns*1  
5.0ns*1  
Maximum data access time (tAC) from  
24  
clock at CL = 4  
-5C  
0
1
0
1
0
0
0
0
50H  
0.5ns*1  
-4A  
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
60H  
50H  
0.6ns*1  
5.0ns*1  
25  
26  
27  
28  
29  
30  
Minimum clock cycle time at CL = 3  
Maximum data access time (tAC) from  
clock at CL = 3  
Minimum row precharge time (tRP)  
Minimum row active to row active  
delay (tRRD)  
Minimum /RAS to /CAS delay (tRCD)  
Minimum active to precharge time  
(tRAS)  
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
1
0
1
0
0
1
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
60H  
3CH  
28H  
3CH  
28H  
0.6ns*1  
15ns  
10ns  
15ns  
40ns  
Data Sheet E0553E21 (Ver. 2.1)  
5