EBE25UD6ABFA
Block Diagram
/CS0
/CS
R
S1
R
S1
R
S1
/CS
R
S1
R
S1
R
S1
/DQS0
DQS0
DM0
/DQS4
DQS4
DM4
/LDQS
LDQS
LDM
/LDQS
LDQS
LDM
8
8
8
8
R
R
R
R
R
R
S1
S1
S1
S1
S1
I/O0 to I/O7
/UDQS
DQ0 to DQ7
/DQS1
DQ32 to DQ39
/DQS5
I/O0 to I/O7 D2
S1
D0
/UDQS
R
S1
R
S1
R
S1
UDQS
UDM
DQS1
DQS5
UDQS
UDM
DM1
DM5
R
S1
DQ8 to DQ15
I/O8 to I/O15
DQ40 to DQ47
I/O8 to I/O15
/CS
R
S1
R
S1
R
S1
/CS
R
S1
R
S1
R
S1
/DQS2
/DQS6
/LDQS
/LDQS
DQS2
DM2
DQS6
DM6
LDQS
LDM
LDQS
LDM
8
8
8
8
R
R
R
R
R
S1
S1
S1
S1
S1
I/O0 to I/O7
DQ16 to DQ23
DQ48 to DQ55
I/O0 to I/O7 D3
R
S1
R
S1
R
S1
/UDQS
UDQS
D1
/DQS3
DQS3
DM3
/DQS7
DQS7
DM7
/UDQS
UDQS
UDM
UDM
R
S1
R
S1
DQ24 to DQ31
I/O8 to I/O15
DQ56 to DQ63
I/O8 to I/O15
R
R
S2
BA0 to BA1
A0 to A12
BA0 to BA1: SDRAMs (D0 to D3)
A0 to A12: SDRAMs (D0 to D3)
Serial PD
S2
SDA
SDA
R
S2
R
S2
R
S2
SCL
SA0
SCL
A0
/RAS
/CAS
/WE
/RAS: SDRAMs (D0 to D3)
/CAS: SDRAMs (D0 to D3)
/WE: SDRAMs (D0 to D3)
CKE: SDRAMs (D0 to D3)
ODT: SDRAMs (D0 to D3)
U0
A1
SA1
SA2
A2
WP
CKE0
ODT0
Notes :
1. DQ wiring may be changed within a byte.
VDDSPD
VREF
SPD
2. DQ, DQS, /DQS, ODT, DM, CKE, /CS relationships
must be meintained as shown.
SDRAMs (D0 to D3)
3. Refer to the appropriate clock wiring topology under
the DIMM wiring details section of this document.
VDD
SDRAMs (D0 to D3) VDD and VDDQ
VSS
SDRAMs (D0 to D3) SPD
* D0 to D3 : 512M bits DDR2 SDRAM
U0 : 2k bits EEPROM
Rs1 : 22
Ω
Ω
Rs2 : 10
Preliminary Data Sheet E0534E11 (Ver. 1.1)
8
ELPIDA [ ELPIDA MEMORY ]
